A package board, including a core layer and built-up layers and carrying a semiconductor chip and a BGA (ball grid array) terminal on its one major surface and on its opposite major surface, respectively, with an electrode of the semiconductor chip being extended to the BGA surface, has been in extensive use, because the power supply and the ground are provided as planes or layers, with the inductance and the noise being small. However, with increase in the operating frequency of the LSIs in these days, the power supply noise and the ground noise have increased. In particular, the simultaneous switching noise has become of a serious problem.
Reference will now be made to FIG. 6. When a plural number of output buffers become HIGH simultaneously, with the driving waveforms of the output buffers then simultaneously becoming HIGH from LOW, plural signal currents are changed simultaneously. At such time, as the driving currents are changed, the simultaneous switching noise ΔV=n×L×di/dt, where n denotes the number of lines of signals switched simultaneously (the number of signals switched) and L denotes the power supply inductance, is generated due to power supply impedance (inductance component L). In case a semiconductor chip has larger numbers of pins and is run at an extremely high speed, as when the chip has tens of IO ports and is run at an operating frequency (transfer speed) as high as several GHz, it becomes highly desirable to decrease the simultaneous switching noise.
Meanwhile, as stated in detail in Patent Document 1, if there is a signal line on a ground plane or layer and signal current flows on such signal line, the return current flows in a direction opposite to the signal current flow direction. The signal current generates an electromagnetic field in a direction perpendicular to its proceeding direction. This electromagnetic field is coupled to an electromagnetic field generated by the return current at a location directly below the signal line, with the inductance at a location directly below the signal line being low. Since the inductance of the ground plane directly below the signal line is low, the return current flows through a region directly below the signal line in a concentrated fashion. The relationship between the return current and non-coupled current will now be explained. The non-coupled current means the current which is not electromagnetically coupled to the signal current. On the other hand, non-coupled inductance means inductance proper to the non-coupled current. The ground planes, facing each other, are interconnected by ground through-holes, while the signal lines are interconnected by signal through-holes and passed through the ground plane. When the current flows through the signal lines, the return current flows on the ground plane in a reverse direction to the signal current flow direction. This return current, flowing in an area directly below the signal line, by the coupled electromagnetic field, is not coupled with the electromagnetic field of the non-coupled current, flowing towards the ground through-hole, and hence the inductance (non-coupled inductance) is increased. That is, if there flows much uncoupled current, the ground inductance is increased. Since the uncoupled current in an amount corresponding to the amount of the signal current, the amount of the uncoupled current is increased in case there are a number of the signal through-holes larger than the number of the ground through-holes. If a plural number of the non-coupled currents are concentrated to a sole ground through-hole, current paths are overlapped. It has been known that the inductance, increased in direct proportion to the distance between the signal through-hole and the ground through-hole, is increased by units of times, for the same distance, depending on the state of the current overlap. Hence, it has been recognized to be crucial to reduce the distance between the signal through-hole and the ground through-hole, and to increase the number of the ground through-holes compared to that of the signal through-holes. In the Patent Document 1, there is disclosed an arrangement of through-holes in which, of the through-holes lying around signal through-holes, those lying at diagonal positions are adapted to communicate with the power supply or the ground.
Moreover, there is generated voltage drop due to resistance components of the power supply plane and to resistance components of the ground plane, as shown in FIG. 7, whereby the high potential side power supply voltage is lowered, while the low potential side power supply voltage is floated. Hence, with the decrease in the voltage of the semiconductor device, the resistances of the power supply and the ground plane become a problem.
In the designing of the package board and a printed wiring board, a variety of analyses of power supply impedances, employing a tool for analysis of an electromagnetic field, have so far been conducted for reducing the switching noise and for coping with electro-magnetic coupling EMC. A method and an apparatus for designing a printed circuit board are disclosed in Patent Document 2. In this method and apparatus, the layout information for a printed circuit board, e.g. mounting positions for active devices, such as the ground plane, power supply plane, an LSI or an IC, and decoupling capacitors, are input and, using this input information, a circuit model for calculating voltage distribution between the power supply plane and the ground plane is generated. A particular frequency is then selected and, at this particular frequency, the voltage distribution of the power supply plane and the ground plane is calculated. The voltage distribution, thus calculated, is displayed on a two-dimensional voltage map in accordance with the shape of the printed circuit board. Using this voltage map, the arraying positions of the via-holes for signal interconnections across the power supply layer and the ground layer are determined. The technique of formulating a power supply analysis model is also disclosed in Patent Document 3. In this technique of formulating the power supply analysis model, CAD data are converted into data convenient for power supply noise analyses. In case of overlap of power supply islands, i.e. power supply patterns, present in different layers, these overlapping power supply islands are extracted as power supply pairs. The power supply pairs are each divided into meshes, and wavefront patterns, which are wavefronts per wavelength of electromagnetic waves, radiated from the devices on the power supply pair areas to the power supply pair areas, are arrayed. In these power supply pair areas, nodes are arrayed, and impedance parameters (L, R and C), interconnecting the different nodes, are calculated. Using these impedance parameters, the different nodes are interconnected to formulate a power supply layer model.
[Patent Document 1]
JP Patent Kokai Publication No. JP-P2005-19765A
[Patent Document 2]
JP Patent Kokai Publication No. JP-P2001-147952A
[Patent Document 3]
JP Patent Kokai Publication No. JP-P2004-334654A